Accellera Endorses UVM-MS 1.0 Standard for AMS Verification

Accellera has officially approved the Universal Verification Methodology for Mixed-Signal 1.0 standard, a significant milestone aimed at enhancing verification processes for analog and mixed-signal designs. The new standard, built upon the UVM IEEE Std. 1800.2, represents a unified approach to AMS verification, offering improved consistency, efficiency, and accuracy for engineers working across a wide range of semiconductor and electronic systems.

This new methodology aims to streamline the verification of complex mixed-signal designs, which combine both analog and digital components, a task traditionally challenging due to the differing nature of these components. The UVM-MS 1.0 standard is expected to facilitate better integration and verification of AMS systems, particularly in industries such as automotive, telecommunications, and consumer electronics, where mixed-signal designs are commonplace.

Developed by Accellera’s Mixed-Signal Working Group, UVM-MS 1.0 extends the capabilities of the original UVM standard, which has become widely adopted in the digital domain. The standard introduces tailored verification methods and tools specifically designed to address the unique challenges posed by mixed-signal environments, including the need for co-simulation of both analog and digital signals.

At the core of UVM-MS 1.0 is its ability to bridge the gap between digital and analog domains within the verification process. While digital verification methodologies have been well established, the verification of analog components has historically relied on separate, often fragmented methodologies. The UVM-MS 1.0 standard combines these approaches, offering a seamless flow from digital verification through to analog validation. This comprehensive approach not only reduces the time and effort required to verify mixed-signal designs but also improves the overall quality of the final product.

The approval of UVM-MS 1.0 follows a rigorous development process involving contributions from various stakeholders in the semiconductor and design verification industries. Industry experts have expressed strong support for the new standard, recognising its potential to address the increasing complexity of AMS systems. The UVM-MS methodology is expected to promote greater collaboration among engineers, enabling more efficient and effective verification of complex designs, from initial design stages to final testing.

A key benefit of the new standard is its adaptability. UVM-MS 1.0 is designed to be compatible with existing tools and methodologies, allowing engineers to integrate the standard into their existing workflows without significant disruption. The flexibility of UVM-MS 1.0 means it can be applied to a wide variety of applications, from early-stage prototyping to full-scale production, across different industries and technologies.

Another important aspect of the UVM-MS 1.0 standard is its emphasis on automation. The verification of mixed-signal designs often involves extensive manual effort, which can lead to delays and errors. UVM-MS 1.0 introduces automation features that allow for the more efficient generation of testbenches, reducing the need for manual intervention. This automation not only speeds up the verification process but also enhances the accuracy and consistency of testing, ensuring that all components of the AMS system function as expected.

While the standard promises significant benefits, it also highlights the growing need for standardisation in the verification of mixed-signal designs. As AMS designs become increasingly complex, companies must rely on proven, repeatable methodologies to ensure the reliability of their products. UVM-MS 1.0 offers a solution to this challenge, providing a robust framework for ensuring that verification processes are consistent and efficient.