The processor, created by a research team led by Peking University in collaboration with the Shanghai Institute of Microsystem and Information Technology under the Chinese Academy of Sciences, uses phase-change memristors to perform calculations at speeds comparable with the millisecond timescale of biological neural activity.
The findings were published in Science under the title “A sub-10-millisecond neural dynamical system based on phase-change memristors.” The work was led by Professor Yang Yuchao and involved specialists in integrated circuits, materials science, artificial intelligence and computational modelling.
Tests showed that the 40-nanometre chip completed a single neural-dynamics computation in 2.12 milliseconds while maintaining an error tolerance of 10⁻⁷. Its processing speed was between 3.82 and 36.27 times higher than that of advanced application-specific integrated circuits used for comparable workloads.
The device also consumed between 11.75 and 24.73 times less power than those accelerators. In end-to-end tests involving high-fidelity surface reconstruction, its measured and simulated performance exceeded that of Nvidia’s A100 graphics processing unit by between 50.38 and 478.18 times.
The comparisons apply to specialised neural dynamical system workloads rather than general-purpose artificial intelligence processing. The experimental processor is not designed to replace commercial graphics chips across tasks such as large language model training, gaming or conventional data-centre computing.
Neural dynamical systems combine neural networks with differential equations to model how objects, signals or biological structures change over time. Such systems can be used to reconstruct anatomical surfaces, simulate physical processes and interpret data whose shape and behaviour evolve continuously.
Current implementations often rely on graphics processors or conventional digital accelerators. These machines repeatedly transfer information between memory and processing units while adjusting numerical integration steps, creating delays that can extend into hundreds of milliseconds.
The new architecture carries out key operations directly inside memory. Its phase-change memristors can retain multiple electrical conductance levels, allowing stored values to participate in calculations without being moved repeatedly between separate components.
Phase-change memory typically stores information by switching materials between amorphous and crystalline states, which have different levels of electrical resistance. The researchers instead exploited conductance drift — usually treated as an unwanted source of instability — as a controllable physical process for representing neural dynamics.
Combining this behaviour with multilevel in-memory computation allowed the chip to solve parts of the underlying equations through its own material properties. A pipelined design enabled different stages of the calculation to operate in parallel, reducing the time required for repeated numerical operations.
The prototype was demonstrated on surface-reconstruction tasks, including the modelling of complex cortical structures. Producing accurate three-dimensional representations of the brain requires dense, smooth and continuously differentiable deformation fields while preserving the topology of the original surface.
Faster reconstruction could support medical systems that need to update anatomical models as new information arrives. Possible applications include surgical navigation, brain-computer interfaces, robotics, autonomous systems and digital representations of organs or physical environments.
Millisecond-scale computation is particularly important for neural interfaces because electrical activity in the nervous system changes rapidly. Delays introduced by conventional computing platforms can restrict the ability of a system to interpret signals and respond while biological processes are still unfolding.
The study also reflects a wider shift towards analogue and in-memory computing as developers seek alternatives to the conventional separation of processors and memory. Moving data between those components has become a major source of power consumption and latency in artificial intelligence hardware.
Memristors are being studied as artificial synapses because their electrical resistance can change according to previously applied signals. Their compact structure and ability to combine storage with computation make them candidates for energy-efficient neuromorphic processors.
Significant engineering barriers remain before the experimental platform can be deployed commercially. Analogue hardware can be affected by fabrication variations, electrical noise, temperature changes, device ageing and differences between individual memory cells.
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