The additions, announced on Monday, expand Google’s eighth-generation Tensor Processing Unit portfolio to four systems this year. They target different requirements emerging as businesses deploy autonomous AI agents, including protection of proprietary information and the ability to process exceptionally long sequences of data.
TPU 8tx uses the same underlying silicon as Google’s TPU 8t but combines it with fifth-generation AMD EPYC host processors and hardware-enforced security. Google says the architecture protects sensitive data and model parameters while computations are being performed, rather than only when information is stored or transmitted.
The system is intended for government organisations, regulated businesses and other customers handling confidential material. Its applications include running AI models, adapting them with private datasets and training agents without transferring sensitive information between separate computing clusters.
Google says TPU 8tx also incorporates its low-latency Boardfly networking technology, delivering up to twice the latency performance of TPU 8t, with negligible overhead from the security measures. Those figures are company claims, and independently verified performance comparisons have not been published.
AMD confirmed that its EPYC processors provide the host computing foundation, managing data preparation, workload coordination and communication with Google’s accelerators. The companies describe the arrangement as the first cloud TPU system offering hardware-enforced confidential computing.
Dan McNamara, AMD’s senior vice-president and general manager for Compute and Enterprise AI, said the collaboration combined processor performance, memory bandwidth and connectivity with protection for demanding AI workloads. AMD’s security technology is designed to help isolate information during execution, an increasingly important consideration for organisations processing commercially sensitive records.
The second system, TPU 8i Max, addresses a different constraint. Google has placed two TPU 8i chips in one package, doubling computing capability, on-chip static random-access memory and high-bandwidth memory throughput compared with the standard TPU 8i configuration.
The design is intended to support models working across large context windows, where substantial volumes of text, software code, video or other material must remain accessible during processing. Google says it also doubles the amount of accelerator silicon within an existing rack footprint, increasing computing density without requiring proportionately more floor space.
Such workloads can involve multiple AI agents examining an entire software repository or analysing lengthy recordings. Memory bandwidth can become a limiting factor because processors need rapid access to information as they generate responses or coordinate successive tasks.
The stated doubling of hardware resources does not necessarily translate into twice the speed for every application. Actual results depend on software, data movement and the extent to which workloads can use the additional processing and memory capacity.
Amin Vahdat, Google’s senior vice-president and chief technologist for AI and infrastructure, said customer requirements increasingly influence the company’s accelerator designs. The new offerings are system configurations built around existing chips, rather than entirely new silicon architectures, allowing Google to alter networking, packaging and security for specific applications.
Google’s earlier eighth-generation TPU 8t focuses on training large foundation models, while TPU 8i targets low-latency inference and reasoning. The company claims improvements of up to 2.7 times in training performance and 80 per cent in inference price-performance respectively against its preceding generation, although those comparisons are not independent benchmarks.
Google says its TPU business now serves nearly 100 customers, spanning AI laboratories, financial trading firms, retailers and universities. Its accelerators support Google’s Gemini models and are offered through Google Cloud, while the company has also expanded arrangements for customers to install TPU equipment in their own data centres.
The announcement adds another dimension to competition for AI infrastructure spending, where Nvidia’s graphics processors remain a major alternative and AMD supplies both CPUs and AI accelerators. Google’s approach combines proprietary accelerator chips with networking, memory and software designed for particular computing tasks.
Google is also working to make its accelerators easier for developers to use through improvements to software compatibility, including support for PyTorch. The initiative is intended to reduce the engineering effort required to move applications onto TPUs and broaden access beyond specialist AI research teams.
Google did not specify prices, delivery dates or geographic availability for either new system. It also provided no named customer deployments or independently measured comparisons with competing accelerator platforms in Monday’s announcement.
Follow Arabian Post
Select Arabian Post as your preferred source on Google and MSN News for trusted business news and Arab politics and updates.
