Xen 4.20 Debuts with Enhanced Security, Performance, and Expanded CPU Support

The Xen Project has announced the release of Xen 4.20, the latest iteration of its open-source type-1 hypervisor, introducing significant enhancements in security, performance, and hardware compatibility. This version, developed over seven months, underscores the project’s commitment to providing a robust and versatile virtualization platform.

A cornerstone of Xen 4.20 is its bolstered security framework. The integration of the Undefined Behaviour Sanitiser by default across x86, Arm64, RISC-V, and PowerPC architectures aims to detect and mitigate potential code vulnerabilities during the development phase. Additionally, the project has enhanced compliance with the MISRA C standard by incorporating the ECLAIR MISRA C scanner into its continuous integration pipeline, enforcing 90 rules with zero unjustified violations.

Performance optimizations are evident in this release. Notably, support for Last Level Cache coloring on Arm architectures has been introduced, allowing for more granular control over cache allocation and improved performance in specific workloads. The hypervisor also now supports Intel’s Extended Page Tables Paging-Write feature, enhancing memory management efficiency on Intel processors.

Hardware compatibility has been significantly broadened. Xen 4.20 includes support for AMD’s Zen 5 processors, ensuring users can leverage the latest advancements from AMD within their virtualized environments. Experimental support for Armv8-R has also been introduced, expanding Xen’s applicability in real-time computing scenarios. Furthermore, the hypervisor now accommodates the NXP S32G3 processor family and includes a driver for NXP’s LINFlexD UART, catering to the automotive and embedded systems sectors.