Florence, based on the planned Zen 7 architecture, is targeted for 2028 as part of AMD’s seventh-generation EPYC processor family. It is scheduled to be followed by Ravenna, an eighth-generation EPYC platform using Zen 8 cores, in 2030.
The disclosure gives data-centre operators an unusually long view of AMD’s development plans as competition intensifies across processors, accelerators, networking and complete computing systems. Intel is rebuilding its server roadmap, while Nvidia is expanding beyond graphics processors into central processing units designed for large AI installations.
AMD has not formally identified the manufacturing process planned for Florence. Industry speculation has linked the processor to technology more advanced than the 2-nanometre class, potentially involving a sub-2nm production node. That remains unconfirmed and could change as foundry schedules, chip designs and commercial requirements develop.
Ravenna is at an earlier stage. AMD has confirmed that the architecture is under development and has placed it on a 2030 timeline, but has released few details about its core counts, memory system, packaging or manufacturing process.
The roadmap follows the production ramp of Venice, AMD’s sixth-generation EPYC processor and the first high-performance computing product to enter volume production using Taiwan Semiconductor Manufacturing Company’s 2nm technology. Manufacturing began in Taiwan, with production planned to expand later to TSMC’s fabrication operations in Arizona.
Venice is built around AMD’s Zen 6 architecture and is designed for cloud services, enterprise computing, scientific workloads and AI infrastructure. The leading EPYC 9996 configuration offers as many as 256 cores and 512 processing threads, doubling the maximum core count available in several earlier server configurations.
The platform supports up to 16 memory channels and as much as 1.6 terabytes per second of memory bandwidth when equipped with advanced memory modules. It also provides up to 160 PCI Express 6.0 lanes, allowing servers to connect large numbers of accelerators, storage devices and network interfaces.
AMD says Venice can deliver substantially higher computing performance than its Turin generation while improving the amount of work completed for each watt of electricity consumed. These efficiency gains have become increasingly important as AI data centres face limits involving power availability, cooling infrastructure and operating costs.
A specialised Venice-X processor is planned for the second half of 2027. It will combine 96 high-frequency Zen 6 cores with more than 1.1 gigabytes of stacked L3 cache, targeting scientific computing, engineering simulation, electronic design automation and other workloads that benefit from rapid access to large datasets.
Florence is expected to extend this strategy by introducing Zen 7 cores, additional AI-oriented instructions and more advanced memory capabilities. The processor is also being developed as part of a wider family of purpose-built computing platforms rather than as a standalone server chip.
That family includes Ferrara, designed as an AI host node, and Faenza, described as an environment for agentic AI applications. The approach reflects a shift in the data-centre market towards systems optimised for particular workloads instead of general-purpose servers performing every task.
Central processors remain essential even as graphics accelerators absorb a greater share of AI computation. CPUs manage operating systems, storage, networking, security, data preparation and the scheduling of work across multiple accelerators. Agentic AI systems may increase those demands because they rely on large numbers of simultaneous software processes and frequent movement between models, databases and external services.
AMD expects the market for data-centre computing products to exceed $200 billion by 2030. The company is seeking a larger share through annual product updates spanning EPYC processors, Instinct accelerators, Pensando networking technology and rack-scale systems.
Its Helios platform combines Venice processors with MI455X accelerators and high-speed interconnect technology in a complete AI rack. Future versions are expected to incorporate the MI500 accelerator generation, followed by MI600 products around the same 2028 period as Florence.
The roadmap also deepens AMD’s dependence on advanced manufacturing and packaging capacity. TSMC remains a central partner, providing the processes required to produce increasingly dense chiplets and connect them through sophisticated packaging.
Follow Arabian Post
Select Arabian Post as your preferred source on Google and MSN News for trusted business news and Arab politics and updates.
