Huawei schedules two Ascend AI chips for 2027

Huawei Technologies has laid out plans to launch two new artificial intelligence processors in 2027, strengthening its push to supply the computing power China needs as US export controls restrict access to Nvidia’s most advanced chips.

Rotating chairman David Wang said at Huawei Connect 2026 in Shanghai on Thursday that the company plans to release the 960DT in the first quarter of 2027 and the Ascend 960PR in the third quarter. The roadmap places Huawei’s next generation of accelerators at the centre of its effort to build domestic alternatives for training and running increasingly demanding AI models.

Huawei also unveiled the Ascend 960 SuperPoD and an upgraded version of its UnifiedBus interconnect technology, designed to link large numbers of processors so they can function as one computing system. The company said a combination of UnifiedBus and its Hi-ONE optical system could connect as many as 4,000 processors within a SuperPoD, extending high-speed optical links deeper into the machine.

The strategy reflects a broader shift towards system-level performance rather than relying solely on the capability of individual chips. Advanced AI workloads require thousands of processors to exchange data rapidly, making networking bandwidth, memory access and cluster efficiency increasingly important alongside raw chip performance.

Wang said Huawei has developed 11 semiconductors based on UnifiedBus technology for use across its large computing systems. Its biggest planned superclusters will be able to support up to one million AI processors, he said, while the company has already shipped more than 1,000 smaller supernodes to more than 370 customers.

Huawei did not identify those customers or give a detailed breakdown of shipments. It also did not provide independently verified benchmarks directly comparing the new 960-series chips with Nvidia’s leading accelerators, leaving questions over single-chip performance, software compatibility and manufacturing scale.

The company had previously said the Ascend 960 would offer twice the computing power, memory capacity, memory bandwidth and interconnect ports of the Ascend 950 generation. Huawei has also been developing the Atlas 960 SuperPoD and SuperCluster, with the larger system intended to combine more than one million neural processing units when it reaches the market.

Huawei’s current product roadmap also includes the Ascend 950DT, due in the fourth quarter of 2026. The company has said that processor will use its HiZQ 2.0 high-bandwidth memory, providing 144 GB of capacity and 4 terabytes per second of bandwidth. Those specifications are intended to support both model training and the decode stage of inference workloads.

US restrictions have limited China’s access to cutting-edge Nvidia processors and advanced semiconductor manufacturing equipment, giving domestic suppliers greater room to expand. Huawei has emerged as the most prominent of those suppliers, but Nvidia retains a major advantage through its CUDA software ecosystem and a broad global developer base.

Chinese AI developers have increasingly turned to domestic accelerators for inference, where trained models generate responses, even as many frontier laboratories continue to depend on Nvidia hardware for the most demanding training jobs. That split has made Huawei’s ability to improve both hardware and software a critical test of whether China can reduce its dependence on foreign computing infrastructure.

Huawei is also contending with shortages of high-bandwidth memory, a key component in AI accelerators. The company has designed memory for some newer Ascend products, but supply constraints across the industry have increased costs and complicated efforts to scale production quickly enough to meet demand.

The group is seeking to offset those limitations through architectural changes, advanced packaging, optical networking and tighter integration between chips, systems and software. Its SuperPoD approach is intended to compensate for weaker performance from individual processors by allowing much larger numbers of chips to work together with lower latency.



Notice an issue?

Arabian Post strives to deliver the most accurate and reliable information to its readers. If you believe you have identified an error or inconsistency in this article, please don't hesitate to contact our editorial team at editor[at]thearabianpost[dot]com. We are committed to promptly addressing any concerns and ensuring the highest level of journalistic integrity.


Loading next story…