Chip redesign targets data centre losses

A prototype chip developed by engineers at the University of California San Diego has opened a possible new route to cutting energy waste inside data centres, by improving the way power is stepped down for graphics processors that handle artificial intelligence and other high-performance workloads. The team says the design converted 48 volts to 4.8 volts with peak efficiency of 96.2 per cent in laboratory tests, while delivering about four times more output current than earlier piezoelectric-based approaches. The work was published on 8 April in Nature Communications.

The advance matters because power conversion is one of the less visible but more consequential bottlenecks in modern computing. Data centres commonly distribute electricity at higher voltages, while GPUs and other processors need far lower voltages, often between 1 and 5 volts. Each conversion stage creates losses, heat and design trade-offs. As processors become more power-hungry, engineers are under pressure to shrink those losses without making systems bulkier or harder to cool. The International Energy Agency said global electricity consumption by data centres is projected to roughly double to about 945 terawatt-hours by 2030 in its base case, with accelerated servers driven largely by AI accounting for almost half of the net increase.

Conventional step-down converters usually rely on magnetic components such as inductors. Those designs are well understood and widely deployed, but the UC San Diego team argues they are nearing practical limits in applications where large voltage drops and high current demand must be handled in tight spaces. Patrick Mercier, the study’s senior author and a professor of electrical and computer engineering, said engineers had become so adept at designing inductive converters that there was limited room left for major gains from the established approach. That assessment helps explain why researchers are looking again at alternative architectures once considered too immature for mainstream deployment.

The new design centres on a piezoelectric resonator, a small device that stores and transfers energy through mechanical vibrations. Piezoelectric resonators have attracted attention because they can be compact and potentially easier to scale in manufacturing than magnetic parts. Their weakness has been performance at high voltage conversion ratios, where efficiency and current handling tend to deteriorate. The paper describes a hybrid approach that adds flying capacitors and a switched-capacitor output network, creating multiple power-delivery paths while reducing internal charge redistribution losses inside the resonator. In the abstract, the authors say that structure shifted the optimal piezo network conversion from 2:1 to 3:1 and produced a net optimal ratio of 9:1.

That combination of circuit layout and vibrating component is what distinguishes the prototype from prior attempts. According to UC San Diego’s account of the tests, the design not only raised efficiency but also eased the load on the resonator itself by spreading power flow across more than one route. The chip was fabricated in a 180-nanometre high-voltage CMOS process, a detail that suggests the project is still at the prototype and validation stage rather than at the edge of commercial manufacturing. For the data-centre industry, the immediate significance lies less in the exact process node than in the indication that alternative power architectures may still produce meaningful gains even after years of incremental optimisation.

The wider market backdrop makes such work more than an academic exercise. EPRI said last month that data centres could consume 9 per cent to 17 per cent of US electricity by 2030, up from 4 per cent to 5 per cent today, reflecting the sharp build-out of AI infrastructure and other digital capacity. Its brief estimated US data-centre electricity use at 177 to 192 terawatt-hours in 2024, rising to roughly 380 to 790 terawatt-hours by 2030, with localised strain especially acute in major and emerging hubs. Those projections are not direct proof that any one chip design will reshape the sector, but they do show why power conversion losses, once treated as a narrow engineering issue, are moving closer to the centre of the industry’s cost and sustainability debate.

There are still clear limits to the claim. Mercier said piezoelectric-based converters were not yet ready to replace existing power converter technologies in data-centre deployments. He said further progress was needed in materials, circuit design and packaging. One practical complication is that piezoelectric resonators physically vibrate and cannot simply be soldered onto circuit boards using standard methods, which means system integration remains a hurdle. That caveat is important, because laboratory efficiency figures often travel faster than the engineering work needed to make them robust, manufacturable and cost-effective at rack scale.