Novel technique measures warpage in next-gen integrated circuits
Figure 1: An X-ray diffraction image of a chip package containing four multi-stacked silicon die. The thickest silicon die (300 µm thick) is the large flat stripe, which experiences the least warpage as it is glued to the package lead frame (lead frame not imaged). The three “wiggly” strips are individual transmission section images for each of the three remaining die (each 50 µm thick) stacked upon […]



